The present invention relates to a redundancy technique in a semiconductor memory and more particularly, to a semiconductor memory having a redundancy circuit suitable for high-speed operation.
Redundancy in memory cells is a technique conventionally well known for improving yield in semiconductor memory operation. In this technique, spare memory cells are previously provided on a semiconductor chip so that a defective memory cell is replaced by a spare memory cell to thereby improve the product yield. The above replacement is carried out usually on a single- or plural word line or bit line basis.
Meanwhile, in recent semiconductor memories, a memory array for arranging memory cells thereon is often divided (mat division) into a plurality of zones called memory mats or subarrays. This is carried out by such a circuit demand as shortening of a signal delay time or securing of a desired signal-to-noise ratio. When the aforementioned redundancy technique is applied to the mat-divided semiconductor memory, it is common to replace a defective memory mat by a spare line of the same mat. When there are many defects in a single memory mat, however, there occurs such a problem that the number of spare lines becomes insufficient for the memory mat. A method for effectively solving the problem is disclosed in JP-A-59-135700 and JP-A-60-130139. In these Publications, it is suggested that, when there are defects in a memory mat, they may be replaced even by spare lines of other memory mats. Of course, the defects can be replaced even by the spare lines of the same memory mat. With such an arrangement, interchange of the spare lines can be realized between memory mats, thus expectedly improving its yield.